Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD's well below the available light source wavelengths.
One well known technique for improving the resolution performance of current imaging tools is the use of OPC techniques, which include the use of subresolution assist features, also known as scattering bars (SBs), within the mask design. For example, U.S. patent application Ser. No. 10/756,829 filed on Jan. 14, 2004; Ser. No. 10/756,830 filed on Jan. 14, 2004, and Ser. No. 10/878,490 filed Jun. 29, 2004, all of which are assigned to the assignee of the instant application, and all of which are incorporated herein by reference in their entirety, disclose a concept of placing SBs and non-printable phase features in the mask design utilizing interference maps (IM). While the concept has been demonstrated feasible for manufacturing purposes, it can still be a challenging process to apply the concepts into a manufacturing worthy implementation, especially when dealing with complex mask designs.
One such complex mask which is of particular interest is a contact hole mask. Currently there are two well-known resolution enhancement practices when comes to the printing of contact hole (CH) mask patterns with hole dimensions that are less than the exposure wavelength (λ). The most common one is to use predefined rules to bias the contact hole feature on a 6% attenuated phase-shifting mask, which allows the enlarged CH feature to become more printable. This process works sufficiently well for patterning a CH mask with hole dimensions at near or slightly below exposure wavelength.
In order to print yet smaller dimension of contact holes, approaching one-half of the exposure wavelength, the second practice is to add scattering bars around the CH feature in question. The use of SBs enhances the slope of the CH aerial images and thereby achieves a better depth of focus. The placement of SBs in the neighborhood of main CH feature also helps improve the peak intensity level of the main CH feature, thus resulting in better printability. For more uniformed printing for the entire CH mask, it maybe necessary to apply both the feature biasing schemes and SBs at the same time.
The feature “biasing” scheme can be based on either a rule-based optical proximity correction (OPC) or model-based OPC method. The SB application can also be performed either using a rule-based or model-based method. When utilizing a rule-based method, the SB placement and size must be first “manually determined” for as many contact feature pitch ranges as possible. However, in actual practice, it is typically not possible to have enough rules for all random CH pattern conditions for a real IC design. It has been acceptable to utilize a limited set of SB rules together with model-based OPC scheme for the printing of CH dimensions at slightly below the exposure wavelength. However, such a scheme is not trouble free when printing a CH pattern at one-half or smaller of the exposure wavelength. The use of model SB is considered to be much more adequate to reduce the imaging “weak spot” for the entire exposure field.
As noted above, it is known to use interference mapping as a basis for model SB application. FIGS. 1a-1d illustrates an example of the generation of an interference map for an isolated contact illuminated using Quasar™ illumination, which can be generated using either an empirical method or a simulation method as detailed in U.S. patent application Ser. No. 10/756,829 filed on Jan. 14, 2004; Ser. No. 10/756,830 filed on Jan. 14, 2004, and Ser. No. 10/878,490 filed Jun. 29, 2004, all of which are incorporated herein by reference in their entirety. FIG. 1a and 1b illustrate an exemplary binary fresnel lens and CPL fresnel lens, respectively, which correspond to utilizing a binary mask and a chromeless-phase-lithography (CPL) mask, respectively. FIG. 1c illustrates the image intensity utilizing a point spread function (PSF) associated with the isolated contact. In the case of an isolated contact, the interference map is directly proportional to the PSF. FIG. 1d illustrates an exemplary interference map associated with the isolated contact.
As is known, it is possible to identify areas of constructive and destructive interference with respect to the imaging of the given feature with an interference map. Once these areas are identified, scattering bars having the proper phase assigned relative to the main feature, can be placed in the mask design to constructively enhance the printing of the main feature. Referring to FIG. 1d, the yellow and red regions 12 in the interference map represent areas where the zero phase light has the strongest positive affect on the contact imaging. The blue regions 14 represent areas where π-phase shifted light has the strongest positive affect on the contact imaging, and the black regions 16 represent areas where neither π-phase shifted light nor zero phase light have a positive affect on contact imaging.
FIG. 2 is an example of interference map generated for a random 2D IC layout. The green areas 17 in FIG. 2 correspond to the areas in which n-phase shift light enhances imaging of the contact hole and the orange areas 19 correspond to the areas in which zero phase shift light enhances imaging of the contact hole. FIG. 3 shows the placement of SBs based on the IM of FIG. 2. As shown, SBs having a x-phase shift are placed in the green areas 17 of the IM and SBs having a zero phase shift are placed in the orange areas 19 of the IM. However, when utilizing this IM technique in combination with the model-based technique, the number of SBs to be placed in the mask can be increased by at least one to two orders of magnitude, thereby resulting in a significant increase in pattern complexity, as is shown in FIG. 4. It is an objective of this invention to provide a method for applying SBs which allows for the benefits of the foregoing technique but which reduces the SB count and the overall complexity of the mask design.
Another issue associated with imaging contact hole patterns for very low k1, where k1=(numerical aperture, NA, of the exposure tool)*(minimum half pitch of CH mask pattern)/(exposure wavelength, λ), there is typically no room to insert SB between the contact holes. Without the ability to shrink the exposure wavelength, the printability is mostly governed by the NA of the exposure tool. Due to the two dimensional nature of contact hole features, it is more challenging to print low k1 factor contact holes as compared to the printing of one-dimensional line and space patterns. Looking beyond 45 nm IC technology node, it is very likely that the industry will stay with 193 nm immersion for IC manufacturing. The NA for the exposure tool can be made close to 1.4 for water-based immersion. However, the relative low k1 factor issue remains for the printing of two-dimensional contact holes at 32 nm node. Splitting a densely packed contact mask pattern into two or more isolated exposure masks is one logical option for addressing the foregoing issue.
When a contact hole mask is decomposed into two less dense mask patterns, the k1 can be relaxed by as much as a factor of 2. This will allow the use of IM generated SBs along with model-based OPC to achieve the desire printing quality for each mask exposure. The overall printing capability is dependent on the outcome of the double exposure.
There are basically two patterning methods for pitch-decomposed contact hole masks. One is to print the first decomposed mask and then perform the develop and etch process. The first exposure is then unloaded from the wafer chuck of the exposure tool for subsequent processing before it is ready to be re-loaded for the second exposure. With this method, there is no correlation in terms of imaging between the first and second patterning. The imaging process can take a full advantage of high k1 factor except for a stringent alignment requirement since the wafer has left the chuck between the two exposures. With a develop and etch process in between the two patterning exposures, more process related complications can be expected. This method is referred to as double patterning (DP).
The other method is to leave the wafer on the chuck after the first mask exposure, and then re-expose it with the second mask. This method is feasible with a dark field mask since the first exposure does not affect the “dark area” of the first mask and vice versa for the second exposure mask. This exposure technique is referred to as double exposure (DE), and is relatively easier since it does not involve any of the subsequent wafer processing steps between the two exposures. Further, the alignment accuracy requirement between the two mask exposures is straightforward compared to the DP technique because the wafer never leaves the exposure chuck. The main challenge for the DE technique concerns how to “protect” the un-exposed areas in each exposure while ensuring the best printability for the intended patterning areas. This is particularly challenging because SBs are utilized in the unexposed areas. It is a second objective of the present invention to address this issue.